1. Field of the Invention
The present invention relates to a clock supply circuit and method.
2. Description of the Related Art
To an LSI such as a microcontroller, a quartz oscillator or the like is connected to supply clock signals. While the quartz oscillator has merits such that it is cheap, it needs a small mounting area, and the like, it requires a certain time period for its oscillation to be stable. Also, in some cases, an oscillation circuit may be provided inside an LSI. In such cases, similarly, a certain time period is required for its oscillation to be stable.
A time for oscillation to be stable is determined depending on characteristics of an oscillator and an LSI, a temperature, a voltage, resistance or load on a board, and the like. During this oscillation stabilization waiting time, the operation of an LSI is stopped by measuring a certain time period using a counter mounted inside a microcontroller and supplying an initialization signal to the LSI during the certain time period, or by externally supplying a reset signal that includes a sufficient oscillation stabilization waiting time, or the like. The reset signal is negated at the time when the oscillation is considered to be stable, and the LSI starts operating.
FIG. 3 is a diagram showing a configuration example of an LSI including a clock supply circuit, and FIG. 4 is a timing chart showing an operation example thereof.
When a quartz oscillator 301 is connected to an oscillation cell (oscillation circuit) 302 inside an LSI 300, an oscillation signal X oscillates. The oscillation cell 302 has a transistor, and inputs the oscillation signal X and outputs a clock signal CKIN. The clock signal CKIN is a binary signal representing the oscillation signal X by a high level or a low level depending on a threshold voltage of the transistor.
A two-divider 303 is constituted of a flip-flop and divides the clock signal CKIN in two to output a clock signal DIV2. The frequency of the clock signal DIV2 is ½ of the frequency of the clock signal CKIN. The two-divider 303 is provided for making a duty ratio for the clock signal DIV2 to be 50%.
An oscillation stabilization waiting counter 306 is constituted of a plurality of D-type flip-flops, which counts the number of pulses of the clock signal DIV2 and turns a count completion signal CRDY to a high level and outputs it when the number of pulses exceeds a predetermined value. A power supply voltage monitoring circuit 305 monitors stability of a power supply voltage after a start-up by turning on of power, and turns a reset signal PRST to a low level and outputs it when the power supply voltage becomes stable. A reset signal ERST is an external reset signal that is supplied externally.
A reset generating circuit 307 inputs the reset signals PRST, ERST and the count completion signal CRDY, and outputs a system reset signal RST1 and a clock enable signal CLKEN. The clock enable signal CLKEN turns to a high level after the reset signals PRST and ERST turn to a low level and the count completion signal CRDY turns to a high level.
An AND (logical product) circuit 304 outputs a logical product signal of the clock signal DIV2 and the clock enable signal CLKEN as a system clock signal CK1. Specifically, when the clock enable signal CLKEN is at a low level, the system clock signal CK1 is at a low level. When the clock enable signal CLKEN is at a high level, the system clock signal CK1 is the same as the clock signal DIV2. After the clock enable signal CLKEN turns to a high level and supply of the system clock signal CK1 is started, the system reset signal RST1 turns from a high level to a low level. The low level of the system reset signal RST1 indicates that the system clock signal CK1 is usable.
Responding to turning on of the power, the power supply voltage increases, and the quartz oscillator 301 starts oscillating. At this time, the oscillation signal X starts oscillating with a small amplitude at first, which gradually becomes a large stable amplitude. A waveform of the oscillation signal X with a large amplitude becomes the clock signal CKIN having a normal pulse width, but a waveform of the oscillation signal X with a small amplitude may become the clock signal CKIN having a short pulse width. The two-divider 303 divides the clock signal CKIN in two and outputs the clock signal DIV2. At this time, if the clock signal CKIN has a sufficiently large pulse width, the clock signal DIV2 toggles at a rising edge of a pulse of the clock signal CKIN. In other words, by synchronizing with rising of the clock signal CKIN, the clock signal DIV2 logically inverts between a high level and a low level. However, when the clock signal CKIN has a short pulse width, the two-divider 303 may fail to operate, which makes the clock signal DIV2 inconstant.
At the time when the power is turned on, the power supply voltage monitoring circuit 305 asserts (turns to a high level) the reset signal PRST. The oscillation stabilization waiting counter 306 counts the number of pulses of the clock signal DIV2, and turns the count completion signal CRDY to a high level and outputs it when the number of pulses reaches a predetermined value. Note that when the clock signal DIV2 becomes inconstant, the output signal CRDY of the counter 306 does not necessarily become accurate. Therefore, the predetermined value needs to be sufficiently long.
When the reset signal PRST is asserted (turned to a high level), a reset generating circuit 307 asserts (turns to a high level) the system reset signal RST1. When the count completion signal CRDY turns to a high level, the reset generating circuit 307 asserts (turns to a high level) the clock enable signal CLKEN, and starts supplying the system clock signal CK1. Also, thereafter, the reset generating circuit 307 negates (turns to a low level) the system reset signal RST1. An oscillation stabilization waiting time 401 from this turning on of the power until the negating of the system reset signal RST1 needs to be a few milliseconds to a few tens of milliseconds.
In addition, Patent Document 1 listed below describes a clock supply circuit having a PLL output stabilization detecting circuit which detects, when a PLL-type frequency multiplying circuit returns from a clock supply halt state in which it is halted and clock supply is stopped, whether a multiplication clock signal outputted from the PLL-type frequency multiplying circuit is stable or not, and transmits the multiplication clock signal as a system clock signal to an integrated circuit when it detects that the multiplication clock signal is stable.
[Patent document 1] Japanese Patent Application Laid-open No. 2001-313547
The oscillation stabilization waiting time 401 needs to be determined by anticipating the worst value, which is a time that cannot be neglected as a start-up time for the LSI 300. When the quartz oscillator 301 is used, it requires a few milliseconds to a few tens of milliseconds. Therefore, from turning on of the power until the LSI 300 becomes operable, at least a few milliseconds to a few tens of milliseconds are needed.
A program mounted on the LSI such as a microcontroller generally performs initialization of a RAM, development of a program from a low speed ROM to a high speed RAM, and the like immediately after a start-up thereof. After these initialization operations are completed, a main program starts operating. Since also these initialization operations are necessary at the time when turning on the power, a longer time is needed until the main program becomes able to start operating.